?2010 fairchild semiconductor corporation 1 www.fairchildsemi.com march 2010 fds6930b rev. a1 fds6930b dual n-channel logic level powertrench ? mosfet fds6930b dual n-channel logic level powertrench ? mosfet features 5.5 a, 30 v. r ds(on) = 38 m ? @ v gs = 10 v r ds(on) = 50 m ? @ v gs = 4.5 v fast switching speed low gate charge high performance trench technology for extremely low r ds(on) high power and current handling capability general description these n-channel logic level mosfets are produced using fairchild semiconductors advanced powertrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. these devices are well suited for low voltage and battery pow- ered applications where low in-line power loss and fast switch- ing are required. absolute maximum ratings t a = 25c unless otherwise noted package marking and ordering information symbol parameter ratings units v dss drain-source voltage 30 v v gss gate-source voltage 20 v i d drain current C continuous (note 1a) 5.5 a C pulsed 20 p d power dissipation for dual operation (note 1) 2 w power dissipation for single operation (note 1a) 1.6 (note 1b) 1 (note 1c) 0.9 t j , t stg operating and storage junction temperature range C55 to 150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r jc thermal resistance, junction-to-case (note 1) 40 c/w device marking device reel size tape width quantity fds6930b fds6930b 13" 12mm 2500 units d1 d1 d2 d2 s1 g1 s2 g2 pin 1 so-8 4 5 3 6 2 7 1 8
2 www.fairchildsemi.com fds6930b rev. a1 fds6930b dual n-channel logic level powertrench ? mosfet electrical characteristics t a = 25c unless otherwise noted notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is de?ned as the sol der mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0% 3. trr parameter will not be subjected to 100% production testing. symbol parameter test conditions min typ max units off characteristics bv dss drainCsource breakdown voltage v gs = 0 v, i d = 250 a30 v ? bv dss ? t j breakdown voltage temperature coef?cient i d = 250 a, referenced to 25 c 26 mv/ c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v v ds = 24 v, v gs = 0 v, t j = 55 c 1 10 a i gss gateCsource leakage v gs = 20 v, v ds = 0 v 100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.9 3 v ? v gs(th) ? t j gate threshold voltage temperature coef?cient i d = 250 a, referenced to 25 c C4.6 mv/ c r ds(on) static drainCsource onCresistance v gs = 10 v, i d = 5.5 a v gs = 4.5 v, i d = 4.8 a v gs = 10 v, i d = 5.5 a, t j = 125 c 31 40 45 38 50 62 m ? i d(on) onCstate drain current v gs = 10 v, v ds = 5 v 20 a g fs forward transconductance v ds = 5 v, i d = 5.5 a 19 s dynamic characteristics c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 310 412 pf c oss output capacitance 90 120 pf c rss reverse transfer capacitance 40 60 pf r g gate resistance v gs = 15 mv, f = 1.0 mhz 1.9 ? switching characteristics (note 2) t d(on) turnCon delay time v dd = 15 v, i d = 1 a, v gs = 10 v, r gen = 6 ? 612 ns t r turnCon rise time 612 ns t d(off) turnCoff delay time 16 28 ns t f turnCoff fall time 24 ns q g total gate charge v ds = 15 v, i d = 5.5 a, v gs = 5 v 2.7 3.8 nc q gs gateCsource charge 1.0 nc q gd gateCdrain charge 0.7 nc drainCsource diode characteristics and maximum ratings i s maximum continuous drainCsource diode forward current 1.3 a v sd drainCsource diode forward voltage v gs = 0 v, i s = 1.3 a (note 2) 0.8 1.2 v t rr diode reverse recovery time (note3) i f = 5.5 a, d if /d t = 100 a/s 16 32 ns q rr diode reverse recovery charge 6 nc a) 78c/w when mounted on a 0.5 in 2 pad of 2 oz copper b) 125c/w when mounted on a 0.02 in 2 pad of 2 oz copper c) 135c/w when mounted on a minimum pad.
3 www.fairchildsemi.com fds6930b rev. a1 fds6930b dual n-channel logic level powertrench ? mosfet typical characteristics 0 4 8 12 16 20 0 0.5 1 1.5 2 v ds , drain to source voltage (v) i d , drain current (a) v gs = 10v 4.5v 3.5v 4.0v 3.0v 6.0v 0.8 1 1.2 1.4 1.6 1.8 2 048121620 i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = 3.5v 4.5v 5 . 0 v 6.0v 10.0v 4.0v figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. 0.6 0.8 1 1.2 1.4 1.6 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = 5.5a v gs = 10.0v 0.02 0.04 0.06 0.08 0.1 0.12 246810 v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = 2.75a t a = 125 c t a = 25 c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 4 8 12 16 20 12345 v gs , gate to source voltage (v) i d , drain current (a) t a = 125 c 25 c -55 c v ds = 5v 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 v sd , body diode forward voltage (v) i s , reverse drain current (a) v gs = 0v t a = 125 c 25 c -55 c figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature.
4 www.fairchildsemi.com fds6930b rev. a1 fds6930b dual n-channel logic level powertrench ? mosfet typical characteristics 0 2 4 6 8 10 0123456 q g , gate charge (nc) v gs , gate-source voltage (v) i d = 5.5a v ds = 5v 15v 10v 0 100 200 300 400 500 0 5 10 15 20 v ds , drain to source voltage (v) capacitance (pf) c iss c oss c rss f = 1 mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.01 0.1 1 10 100 0.01 0.1 1 10 100 v ds , drain-source voltage (v) i d , drain current (a) dc 10s 1s 100ms 100 s r ds(on) limit v gs = 10.0v single pulse r ja = 135 c/w t a = 25 c 10ms 1ms 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 t 1 , time (sec) p(pk), peak transient power (w) single pulse r ja = 135 c/w t a = 25 c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transient thermal resistance r ja (t) = r(t) * r ja r ja = 135 c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p(pk) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design.
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